XMC-7KWP: User-Configurable Kintex-7 FPGA Modules with Dual SFP+ Ports Description
Acromag’s XMC-7KWP modules feature a high performance user-configurable Xilinx® Kintex®-7 FPGA enhanced with high-speed memory and a high throughput serial interface. The result is a powerful and flexible I/O processor module that is capable of executing custom instruction sets and algorithms.
The logic-optimized FPGA is well-suited for a broad range of applications. Typical uses include hardware simulation, communications, in-circuit diagnostics, military servers, signal intelligence, and image processing. For security, the FPGA’s configuration flash is write-protected.
Two versions of this module are available, offering a choice of an FPGA device with 325k or 410k logic cells.
Front I/O adds dual SFP+ ports and a VHDCR connector. The two SFP+ ports each provide a copper or fibre interface of up to 10.3125Gbps. They also support a Gigabit Ethernet interface. The VHDCR connector interfaces JTAG, USB, and 22 SelectIO.
The rear I/O provides 4-lane high-speed serial interface on the P16 XMC port for customer-installed soft cores. P16 also supports 34 SelectIO channels. The P4 port adds another 60 SelectIO and global clock lines. SelectIO signals are Kintex-7 FPGA I/O pins that support single-ended I/O (LVCMOS, HSTL, SSTL) and differential I/O standards (LVDS, HT, LVPECL, BLVDS, HSTL, SSTL).
With Acromag’s Kintex-7 FPGA modules, you can greatly increase DSP algorithm performance for faster throughput using multiple channels and parallel hardware architectures. Free up CPU cycles by offloading algorithmic-intensive tasks to the FPGA co-processor.
These modules are ideal for high-performance customized embedded systems. Optimize your system performance by integrating high-speed programmable
logic with the flexibility of software running on MicroBlaze
soft processors.
Acromag’s Engineering Design Kit provides software utilities and example VHDL code to simplify your program development and get you running quickly.
A JTAG interface enables on-board debugging. Additional Xilinx tools help finish your system faster. Maximize FPGA performance with Vivado® or ISE®
Design Suite. And with ChipScope Pro tools, you can rapidly debug logic and serial interfaces.
Performance Specifications
FPGA
FPGA device: Xilinx Kintex-7 FPGA. Model XC7K325T FPGA with 326,080 logic cells and 840 DSP48E1 slices or Model XC7K410T with 406,720 logic cells and 1540 DSP48E1 slices.
FPGA configuration: Download via JTAG or flash memory. Installation of 2mm pitch jumper shunt required for writing to flash memory.
Example FPGA program: IP integrator block diagram provided for bus interface, front & rear I/O control, and SDRAM memory interface controller. See EDK kit.
I/O Processing
Front high-speed I/O: Two x1 lanes via SFP+ connectors for Gigabit Ethernet and Fibre Channel interface.
Front user I/O: 36-pin connector provides JTAG connection, USB signals, 2 global differential clock pairs, 11 LVDS signal pairs, and 2 ground signals.
Rear high-speed I/O: 12 high-speed serial lanes. x8 lanes via P15 and x4 lanes via P16.
Rear user I/O: P16: 17 LVDS pairs (34 LVCMOS), 2 global clock pairs. P4: 30 LVDS pairs (60 LVCMOS), 2 global clock pairs.
Engineering Design Kit
Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase of a XMC-7K module (click here for more information).
XMC Compliance
Complies with ANSI/VITA 42.0 specification for XMC module mechanicals and connectors.
Complies with ANSI/VITA 42.3 specification for XMC modules with PCI Express interface.
Electrical/Mechanical Interface: Single-Width Module.
Electrical
XMC PCIe bus interface (P15 and P16): One 114-pin male connector (Samtec ASP-103614-05 or equivalent).
P15 primary XMC connector: 8 differential pairs (PCIe standard, Serial RapidIO, 10-Gigabit Ethernet, or Xilinx Aurora). JTAG.
System Management (XMC provides hardware definition information read by an external controller using IPMI commands and I2C serial bus transactions.)
3.3V power: 4 pins at 1A/pin. 3.3V auxiliary power: 1 pin for system management. Variable power (5V or 12V): 8 pins at 1A per pin.
P16 XMC connector: 4 differential pairs (PCIe, Serial RapidIO, or Xilinx Aurora). 17 LVDS pairs or 34 SelectI/O signals (differential pairs grouped per VITA 46.0 X38s). 2 global clock pairs. Vcco pins are powered by 2.5V and support the 2.5V I/O standards.
P4 PMC rear I/O connector: 64-pin female receptacle header (AMP 120527-1 or equivalent). 64 I/O connections (30 LVDS pairs plus two global clocks). Vcco pins powered by 2.5V and support the 2.5V I/O standards.
VHDCR connector: 36-position connector (Samtec VHDCR-36-01-M-RA) mates with industry-standard VHDCI cable assemblies.
SFP+ host connector: SFP transceiver signals route directly to Kintex-7 FPGA. 10.3125Gb/S maximum data rate. SFP+ copper (Gigabit Ethernet) or fibre optic modules available from Acromag.
JTAG voltage level: 2.5V default. Resistor stuff option for 3.3V (consult factory).
Environmental
Operating temperature: XMC-7KWP-325F: -40 to 55°C. XMC-7KWP-410F: -40 to 55°C.
Storage temperature: -55 to 125°C.
Relative humidity: 5 to 95% non-condensing.
Power: 3.3V (±5%): 7.8W typical. 12V (±5%): 2.7W typical. 3.3V AUX (±5%): 57μW typical.
MTBF: Contact the factory.
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