XMC-VLX: User-Configurable Virtex-5 FPGA Module with Plug-In I/O Description
Acromag’s XMC-VLX boards feature a reconfigurable Xilinx® Virtex
-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCIe interface. Field I/O interfaces to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine AXM plug-in I/O modules.
The result is a powerful and flexible I/O processor module that is capable of executing your custom instruction sets and algorithms.
Three models provide a choice of logic-optimized FPGAs to match your performance requirements. Although there is no limit to the uses for these boards, several applications are ideal. Typical uses include hardware simulation, communications, military servers, in-circuit diagnostics, signal intelligence, and image processing.
64 I/O lines are accessible through the rear (J4) connector. Additional I/O processing is supported on a separate mezzanine card that plugs into the FPGA base board. A variety of these external I/O cards are available to interface for your analog and digital I/O signals.
Large, high-speed memory banks provide efficient data handling. Generous DDR2 SDRAM buffers store captured data prior to FPGA processing. Afterward, data is moved to dual-port SRAM for high-speed DMA transfer to the bus or CPU. Our high-bandwidth PCIe interface ensures fast data throughput.
Take advantage of the conduction-cooled design for use in hostile environments. Conduction efficiently dissipates heat if there is inadequate cooling air flow. Optional extended temperature models operate reliably from -40 to 85°C.
Acromag’s Engineering Design Kit provides software utilities and example VHDL code to simplify your program development and get you running quickly. A JTAG interface enables on-board VHDL debugging.
Learn more about FPGA modules and see all models >
XMC-VLX: User-Configurable Virtex-5 FPGA Module with Plug-In I/O Features & Benefits
- Reconfigurable Xilinx Virtex-5 FPGA
- PCIe bus 4-lane Gen 1 interface
- Supports both front and rear I/O connections
- 64 I/O or 32 LVDS lines direct to FPGA via rear (J4)
- Plug-in I/O modules are available for front mezzanine
- FPGA code loads from PCI bus or flash memory
- Two banks of 1Mb x 32-bit dual-ported SRAM
- Two banks of 32Mb x 16-bit DDR2 SDRAM
- Other memory options available (contact factory)
- Supports dual DMA channel data transfer to CPU/bus
- Support for Xilinx ChipScope
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Pro interface - Conduction-cooled, 0 to 70°C or -40 to 85°C (E versions)
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