PMC-SX: User-configurable Virtex-4 FPGA with plug-in I/O Description
Acromag’s PMC-SX boards use a high-performance Xilinx® Virtex-4
FPGA, but maintain a relatively low price point. They are optimized for high-performance digital signal processing to help you build custom pre/post/co-processing hardware or high-performance filters. You can create more than 40 different functions (MACs, multipliers, adders, and muxes).
Although there is no limit to the uses for Acromag’s FPGA boards, typical applications include sonar and radar processing.
I/O processing is handled on a separate mezzanine card that plugs into the FPGA base board. A variety of these external I/O cards offer an interface for your analog and digital I/O signals. See the AXM I/O Card for more details. Additionally, 64 I/O lines are supported via the rear (J4) connector.
Plenty of DRAM memory is available for receipt and transfer of high-speed data from the I/O data ports on the front and rear of the board. Dual Ported SRAM memory is supplied for storage of data to be passed, via DMA transfer, to the PCI bus. One of the dual ports is attached to the FPGA and the other to the local bus.
The PCI bus interface is handled by a PLX® PCI 9656 device which provides 64-bit 66MHz bus mastering with dual-channel DMA support.
Take advantage of the optional conduction cooling for use in hostile environments. Conduction cooling provides efficient heat dissipation in environments where there is inadequate cooling air flow.
Acromag provides software utilities and examples to simplify your programming and get you started quickly. A JTAG interface enables on-board VHDL simulation.
Learn more about all of Acromag’s FPGA modules and view all models >
PMC-SX: User-configurable Virtex-4 FPGA with plug-in I/O Features & Benefits
- Customizable FPGA (Xilinx Virtex-4 XC4VSX35) withup to 34K logic cells and 192 XtremeDSP
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slices - Supports both front and rear I/O
- Plug-in I/O modules are available for front mezzanine
- 64 I/O lines supported with direct connection to FPGA via rear (J4) connector
- FPGA code loads from PCI bus or flash memory
- 256K x 36-bit dual-ported SRAM
- 32Mb x 32-bit DDR DRAM
- Supports dual DMA channel data transfer to CPU
- Supports both 5V and 3.3V signaling
- Conduction cooled 0 to 70°C operating range
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