APA7-500: Reconfigurable Xilinx® Artix®-7 FPGA Module Description
The APA7-500 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards feature a best in class Artix-7 interface to deliver the industry’s lowest power and high performance.
Designed for COTS applications these FPGA based digital I/O modules deliver user-customizable I/O, high-density, high-reliability, and high-performance at a low cost.
The AcroPack® product line updates our popular Industry Pack I/O modules with a PCIe interface format. This tech-refresh design offers a compact size, low-cost I/O, the same functionality as the existing Industry Pack modules and a rugged form factor.
The APA7-500 series modules are 70mm long. This is 19.05mm longer than the full length mini PCIe card at 50.95mm. The boards width is the same as mPCIe board of 30mm and they use the same mPCIe standard board hold down standoff and screw keep out areas.
A down facing 100 pin Samtec connector mates with the carrier card. Fifty of these pins are available for field I/O signals.
The Engineering Design Kit provides users with basic information required to develop custom FPGA firmware for download to the Xilinx FPGA. Example FPGA design code is provided as a Vivado IP Integrator project for functions such as a one-lane PCI Express interface, DMA, digital I/O control register, and more. Users should be fluent in the use of Xilinx Vivado design tools.
Learn more about the AcroPack Series and view all the models >
APA7-500: Reconfigurable Xilinx® Artix®-7 FPGA Module Performance Specifications
FPGA
FPGA device: Xilinx Artix-7 FPGA Model XC7A50T.
FPGA configuration: Download via flash memory.
Example FPGA program: IP integrator block diagram provided for PCIe bus 1 lane Gen 1 interface, DMA controller, on chip block RAM, flash memory and control of field I/O. See EDK kit.
I/O Processing
Field I/O Interface: PCIe bus 1 lane Gen 1 interface.
I/O Connector: 100 pin field I/O connector.
Engineering Design Kit
Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase of a APA7-500 series module.
PCI Express Base Specification
Conforms to revision 2.0
Lanes: 1 lane in each direction.
Bus Speed: 2.5 Gbps (Generation 1).
Memory: 128k space required. 1 base address register.
Environmental
Operating temperature
Air Cooled with heat sink: -40 to 80°C.
Air Cooled without heat sink: -40 to 70°C.
Conduction Cooled: -40 to 85°C ( A conduction cooled application with an AcroPack requires heatsink model AP-CC-01.)
Storage temperature: -55 to 125°C.
Relative humidity: 5 to 95% non-condensing.
Power: 3.3V (±5%) 500mA typical.
Physical
Length: 70mm.
Width: 30mm.
Learn more about the AcroPack Series and view all the models >
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