PMC-VSX User-configurable Virtex-5 FPGA with Plug-in I/O Description
Acromag’s PMC-VSX boards feature a reconfigurable Xilinx® Virtex
-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCI-X interface. Field I/O interfaces to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine plug-in I/O modules. The result is a powerful and flexible I/O processor module that is capable of executing your custom instruction sets and algorithms.
The on-board FPGA is a DSP-optimized version of the Virtex-5 FPGA. Although there is no limit to the uses for these boards, several applications are ideal. Typical uses include hardware simulation, communications, military servers, in-circuit diagnostics, signal intelligence, and image processing.
64 I/O lines are provided via the rear (J4) connector. Additional I/O processing is supported on a separate mezzanine card that plugs into the FPGA base board. A variety of these external I/O cards offer an interface for your analog and digital I/O signals. See the AXM I/O Card data sheet (Bulletin 8400-458) for more details.
Large, high-speed memory banks provide efficient data handling. Generous DDR2 SDRAM buffers store captured data prior to FPGA processing. Afterward, data is moved to dual-port SRAM for high-speed DMA transfer to the bus or CPU. Our high-bandwidth PCI-X interface ensures fast data throughput.
Take advantage of conduction cooling for use in hostile environments. Conduction efficiently dissipates heat in environments with inadequate cooling air flow. Optional extended temperature models operate from -40 to 85°C.
Acromag’s Engineering Design Kit provides software utilities and example VHDL code to simplify your program development and get you running quickly. A JTAG interface enables on-board VHDL simulation.
Specifications
FPGA
FPGA: Xilinx Virtex-5 FPGA
PMC-VSX95: XC5VSX95T FPGA with 94,208 logic cells and 640 DSP48E slices
FPGA configuration: Download via PCI bus or flash memory.
Example FPGA program: VHDL provided implements local bus interface, control of front and rear I/O, SRAM read/ write interface logic, and SDRAM memory interface controller. Program requires user proficiency with Xilinx software tools. See Engineering Design Kit.
I/O Processing
Acromag AXM I/O modules: for front mezzanine: AXM modules attach to the board for additional I/O lines. Analog and digital I/O AXM modules are sold separately.
Rear I/O: 64 I/O (32 LVDS) lines supported with a direct connection between the FPGA and the rear I/O connector (J4).
Engineering Design Kit
Provides user with basic information required to develop a custom FPGA program. Kit must be ordered with the first purchase of a PMC-VSX module.
PMC Compliance
Conforms to PCI Local Bus Specification, Revision 3.0 and CMC/PMC Specification, P1386.1.
Electrical/Mechanical Interface: Single-Width Module.
PCI Bus Modes: Supports PCI-X at 100MHz, 66MHz and Standard PCI at 66MHz and 33MHz
PCI-X Master/Target: 32-bit or 64-bit interface
Signaling: 3.3V compliant.
Interrupts (INTA#): Interrupt A is used to request an interrupt.
Environmental
Operating temperature: 0 to 70°C or -40 to 85°C (E versions)
Storage temperature: -55 to 105°C.
Relative humidity: 5 to 95% non-condensing.
Power: Consult factory. Operates from 3.3V supply.
MTBF: 630,959 hours at 25°C, MIL-HDBK-217F, Notice 2
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